专利名称 ---【 PREPARATION METHOD FOR MULTI-LAYER TUNNELING JUNCTION THREE-DIMENSIONAL TUNNELING FIELD-EFFECT TRANSISTOR 】

基本信息
申请号
WO2015CN72753
申请日
2015.02.11
公开(公告)号
WO2016127337(A1)
公开(公告)日
2016.08.18
申请(专利权)人
中国科学院微电子研究所
申请人地址
发明人
WANG, Minghua;WANG, Wei;FAN, Xiaohua;LIU, Ming; 专利类型 WO
摘要
A preparation method for a multi-layer tunneling junction three-dimensional tunneling field-effect transistor, comprising: performing mutual overlapping growing on heavily doped p-type or n-type silicon and intrinsic or lightly doped silicon, so as to form a multi-layer surface tunneling junction structure; interconnecting the heavily doped p-type or n-type silicon at one end to serve as a source of the transistor, and interconnecting the heavily doped n-type or p-type silicon to the intrinsic or lightly doped silicon to serve as a drain of the transistor; and growing a dielectric layer and a gate material on a side wall and top of the multi-layer surface tunneling junction structure, so as to form a three-dimensional tunneling field-effect transistor of a multi-gate structure. The three-dimensional tunneling field-effect transistor is suitable for CMOS very large scale integration circuit devices, can realize characteristics of low subthreshold slope, low off-state current and low operating voltage of the tunneling field-effect transistor, and overcome the defects of low on-state current and poor drive capability of a common tunneling field-effect transistor.
主权项

 

IPC信息
IPC主分类号
H01L21/336
IPC分类号
H01L21/336;H01L29/739

 

法律状态信息

 

代理信息
代理机构名称
代理人姓名
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